1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to forming metal gate stacks based on replacement gate processing technology for transistor elements having lower threshold voltages.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
For many device technology generations, the gate electrode structures of most transistor elements has comprised silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate dielectric layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices have turned to gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths of 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate dielectric layer of an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate dielectric layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx), and the like. Furthermore, one or more of a plurality of different non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor, as will be discussed in more detail below. These metal gate electrode materials may include, for example, titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), and the like.
One processing method that has been used for forming high-k/metal gate transistor elements is the so-called “gate last” or “replacement gate” technique. FIGS. 1a-1c depict one illustrative prior art method for forming an HK/MG gate electrode structure based on the replacement metal gate (RMG) technique. More specifically, FIGS. 1a-1c schematically illustrate an “HK-last” RMG technique, wherein the “HK” (i.e., high-k) dielectric layer is formed after the dummy gate electrode has been removed, as will now be described in further detail.
FIG. 1a schematically shows a cross-sectional view of an illustrative semiconductor device 100 comprising an illustrative MOS transistor element 150 in an intermediate manufacturing stage using a replacement gate processing technique, wherein initial device processing steps have been performed based on a dummy gate electrode 109. The semiconductor device 100 of FIG. 1a may comprise a substrate 101, in and above which the illustrative transistor element 150 may be formed based on well-established semiconductor device processing techniques. For example, the transistor element 150 may include a gate electrode structure 110, and the substrate 101 may represent any appropriate substrate on which may be formed a semiconductor layer 103, such as a silicon-based layer, or any other appropriate semiconductor material that may facilitate the formation of the MOS transistor element 150. It should be appreciated that the semiconductor layer 103, even if provided as a silicon-based layer, may include other materials, such as germanium, carbon and the like, in addition to an appropriate dopant species for establishing the requisite conductivity type in an active region 102 of the semiconductor layer 103. Furthermore, in some illustrative embodiments, the transistor element 150 may be formed as one of a plurality of bulk transistors, i.e., the semiconductor layer 103 may be formed on or be part of a substantially crystalline substrate material, while in other cases specific device regions of the device 100 or the entire device 100 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided below the semiconductor layer 103.
As shown in FIG. 1a, the active region 102 is typically enclosed by an isolation structure 104, which in the present example may be provided in the form of a shallow trench isolation that is typically used for sophisticated integrated circuits. In the illustrated embodiment, highly doped source and drain regions 106, including extension regions 105 that usually comprise a dopant concentration less than the highly doped regions 106, are formed in the active region 102. The source and drain regions 106, including the extension regions 105, are laterally separated by a channel region 107. Furthermore, the source and drain regions 106 may also comprise metal silicide contact regions 111, which may facilitate the formation of electrical contacts to the transistor element 150. The gate electrode structure 110 is formed above the channel region 107, and may be made up of the dummy gate electrode 109 which, in the manufacturing stage shown in FIG. 1a, may be separated from the underlying channel region 107 by an ultrathin interfacial layer 108. In a typical replacement metal gate integration scheme, the dummy gate electrode 109 may comprise, for example, polysilicon material, and the ultrathin interfacial layer 108 may comprise silicon dioxide, which may be formed to a thickness of approximately 6-10 Å by performing an oxidation process, such as a wet chemical oxidation process, recipes for which are known in the art.
Additionally, depending on the overall process flow requirements, the gate electrode structure 110 may also comprise sidewall spacer structures 110s on or adjacent to the sidewalls of the dummy gate electrode 109, which, depending on the device requirements and/or the process strategy, may include one, two, or even more spacer elements, such as offset spacers, conformal liners, and the like, which may act as appropriate implantation masks for creating the lateral dopant profile for the highly doped drain and source regions 106 and extension regions 105. The sidewall spacer structures 110s may comprise one or more suitable dielectric materials, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. Furthermore, it should be noted that, in those instances wherein the sidewall spacer structures 110s comprise multiple spacer elements, the materials comprising adjacent spacer elements may be different so as to provide the requisite etch selectivity that may be necessary to obtain the desired dopant profile.
As illustrated in FIG. 1a, the semiconductor device 100 may also comprise an interlayer dielectric (ILD) material layer 112, which may act to electrically isolate the transistor element 150 from any subsequently formed metallization layers (not shown). The interlayer dielectric material layer 112 may comprise one or more of several well-known conventional silicon-based dielectric materials, such silicon dioxide, silicon nitride, silicon oxynitride, and the like. Depending on the device design and overall process flow requirements, the interlayer dielectric material layer 111 may also comprise suitably selected low-k dielectric materials, such as porous silicon dioxide, organic polyimides, or organosilicates such as methyl silsesquioxane (MSQ) and the like, wherein it should be understood that a low-k dielectric material may be considered as a material having a k-value that is approximately 3 or less.
After completion of initial device processing steps, such as, for example, patterning of the dummy gate electrode 109; formation of the sidewall spacer structures 110s; formation of source/drain and extension regions 106, 105; formation of silicide regions 111, and the like, the semiconductor device 100 depicted in FIG. 1a may be exposed to a selective etch process 131 adapted to remove the dummy gate electrode 109 in preparation for forming a replacement metal gate electrode. The etching process 131 results in the removal of the dummy gate electrode 109 and the formation of an opening 113 (see FIG. 1b) in the gate electrode structure 110. In certain embodiments, the etching process 131 may be designed to selectively remove the material of the dummy gate electrode 109 relative to the material compositions of the sidewall spacer structures 110s, the interlayer dielectric material layer 111, and the interfacial layer 108. For example, a dummy gate electrode 109 comprising polysilicon material may be selectively removed using any one of several suitably designed wet etch chemistries well known in the art—such as wet inorganic ammonia, tetramethylammonium hydroxide (TMAH), and the like—without inducing undue damage to the surrounding materials, including the nitride and/or oxide materials comprising the interlayer dielectric material layer 111, the sidewall spacer structures 110s, and the interfacial layer 108. Additionally, well known dry etch recipes, such as fluorine or halogen-based RIE and the like, may also be used, as well as etch sequences that utilize a combination of both wet and dry etch processes.
It should be noted that, depending on the specific etch recipe used, the ultrathin interfacial layer 108 may be partially, or even completely, removed during performance of the etching process 131. In such circumstances, the interfacial layer 108 may be grown and/or re-grown by performing an additional oxidation process similar to that used to initially form the interfacial layer 108, such as a wet chemical oxidation process and the like, thereby ensuring that the interfacial layer 108 has an appropriate thickness, such as in the range of approximately 6-10 Å, prior to proceeding with subsequent processing steps, as discussed below.
FIG. 1b depicts the prior art semiconductor device 100 of FIG. 1a in a further manufacturing stage, after the dummy gate electrode 109 has been removed by the etch process 131. As shown in FIG. 1b, and as an initial step in forming a replacement metal gate electrode, a layer of high-k dielectric material 114, such as hafnium oxide (HfO) and the like, may be formed above the semiconductor device 100—including inside of the opening 113—which thereby serves as a gate dielectric layer of the MOS transistor element 150. The layer of high-k dielectric material 114 may be formed by performing a highly conformal deposition process 132, such as an atomic layer deposition (ALD), a chemical vapor deposition (CVD) process such as metal organic chemical vapor deposition (MOCVD) and the like, thereby forming the layer of high-k dielectric material layer 114 to a thickness ranging from approximately 15-20 Å.
FIG. 1c schematically illustrates the prior art semiconductor device 100 of FIG. 1b in an advanced manufacturing stage, after one or more layers of metal gate electrode material have been formed above the semiconductor device 100 and inside of the opening 113, thereby forming the replacement metal gate electrode 110g. In a typical replacement metal gate (RMG) process flow, a first layer of metal gate material 115 may be formed in the opening 113, the material of which may be selected so as to facilitate the proper control of the device work function, both for P-type and N-type MOS (i.e., PMOS and NMOS) transistor elements. Furthermore, depending on the device type (PMOS or NMOS), work function, and threshold voltage requirements, the first layer of metal gate material 115 may comprise a plurality of sub-layers, each of which may comprise different metal gate material, as listed previously. In the illustrative semiconductor device 100 depicted in FIG. 1c, the first layer of metal gate material 115 may comprise, for example, three sub-layers 115a, 115b and 115c, comprising, for example, TiN, TaN, and TiN, respectively. More or fewer sub-layers, comprising other metal gate materials as listed above, may also be used to obtain the desired operational characteristics of the transistor element 150. Additionally, a second layer of metal gate material 116, such as TiAl and the like, may be formed above the first layer of metal gate material 115 so as to completely fill the opening 113. Thereafter, further device processing may continue so as to remove excess material of the high-k dielectric material layer 114 and the first and second layers of metal gate material 115, 116 formed above the ILD layer 112 and outside of the opening 113 so as to form the replacement metal gate electrode 110g. 
It should be noted that the above described process flow may sometimes result in the threshold voltage (Vt) of the MOS transistor element 150 being higher than desired—in particular, when the MOS transistor element 150 is a PMOS transistor element. Theoretical models indicate that a low threshold voltage (Vt) in HK/MG PMOS transistor elements may be achieved when the oxygen content in the first layer of metal gate material 115, more specifically, in the lower portion of the first TiN sub-layer 115a, close to the interface 110i with the high-k dielectric material layer 114, is relatively high, and when the nitrogen content of the sub-layer 115a peaks near the interface 110i. Prior art processes to address the oxygen content issue incorporate oxygen into the TiN sub-layer 115a by performing a relatively high-temperature thermal oxidation process above 400° C., such as in the range of 450° C. to 1000° C. However, exposing device to a thermal oxidation process above 400° C. can result in a growth and/or re-growth of the interfacial oxide layer 108, thereby increasing the thickness of the interfacial oxide layer 108 by a factor of 2 or more—i.e., up to a thickness of 20 Å or even greater. Furthermore, depending on the temperature at which the thermal oxidation process is performed, the TiN sub-layer 115a may be transformed into titanium oxide (TiO). These two detrimental factors—i.e., the increased thickness of the interfacial oxide layer 108 and the transformation of the TiN sub-layer to TiO—may further contribute to an increased threshold voltage (Vt) of the PMOS transistor element, as well as reduced overall device reliability.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with the typical replacement metal gate process flows, such as that described with respect to FIGS. 1a-1c. The present disclosure relates to process schemes that are directed to avoiding, or at least reducing, the effects of one or more of the problems identified above.